Makefile Implicit Rules

in TEST.example.Makefile

$(PROGRAMS_TO_TEST:%=test.$(TEST).%): \

test.$(TEST).%: Output/%.llvm.bc

  @echo "========================================="

  @echo "Running '$(TEST)' test on '$(TESTNAME)' program"

  wc -c $<

Example 0:

foo := a.o b.o c.o
bar := $(foo:%.o=%.c)

sets ‘bar’ to ‘a.c b.c c.c’.

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$(var:a=b)= take the value of the variable var, replace every a at the end of a word with b in that value, and substitute the resulting string.

http://www.gnu.org/software/make/manual/html_node/Substitution-Refs.html#Substitution-Refs

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Example 1:

all: a b

  @echo all

% : %.c

  @echo gcc -c $< -o $@.o</code>

$make

gcc -c a.c -o a.o

gcc -c b.c -o b.o

all

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% match任何數目的任何字符
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Example 2:

objects = foo.o bar.o

all: $(objects)

  @echo all

$(objects): %.o: %.c

  @echo gcc -c $< -o $@

%.c:

  @echo %c = $@

$make

%c = foo.c

gcc -c foo.c -o foo.o

%c = bar.c

gcc -c bar.c -o bar.o

all
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syntax:
<targets ...>: <target-pattern>: <prereq-patterns ...>
   <commands>
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